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p reliminary W6662CF scanner analog front end publication release date: december 1998 - 1 - revision a1 1. general description the w6662 is a highly integrated ccd/cis analog front end signal processor. it provides the components required for all necessary front-end signal process of a ccd/cis scanner, including a 3- channel input clamp circuit for correlated double sampling (short as cds) mode, a multiplexer to mux 3-channel inputs to a correlated double sampling (cds) circuit, a programmable offset adjusted and gain controlled amplifier, a 12-bit analog-to-digital converter. cds or s&h (sample and hold) of operation modes can be chosen. the device configuration is programmed via 3-wire or 4-wired interface, operation modes, offset and gain value of each channel can be programmed. 2. features 12-bit a/d converter no missing code guaranteed three chann els analog input with clamp circuit individually integrated correlated double sampler (cds) supports contact image sensors (cis) accept ccd/cis sensor with three channel or single channel analog out external offset voltage input for cis reference voltage built-in bandgap reference circuit for cds mode and a/d converter integrated 6-bit programmable gain amplifier (pga) with 3-channel register selected integrated 8-bit offset adjustment with 3-channel register selected 3 mhz sampling rate of offset/gain adjustment circuit three-wired or four-wired serial interface programmable registers readback capability low power cmos device power down mode supported 3/5v digital i/o pin packageed in 48-pin qfp applications: flatbed scanners sheetfeed scanners film scanners
p reliminary W6662CF - 2 - 3. pin configuration fig. 3-1 pin assignments. paout paoutn avdd avss vrdt vrdt vrdb vrdb vref vrdc vinr avss ving avss vinb avss cisref cdsck1 adcclk cdsck2 drvss drvdd avdd sel0 sclk sdi/sdio sdo/sms sen dout0 dout1 dout2 dout3 dout4 avss avdd dout6 dout7 dout8 dout9 dout10 dout11 oen 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 dout5 sel1 nc nc nc nc 45 46 47 48 W6662CF winbond 4. block diagram fig. 4 the block diagram of w6662 device. clamp mux 12-bit adc serial i/o port control bandgap reference circuit clamp gain/offset adjust clamp vinr ving vinb cdsck1 cdsck2 dout[11:0] sclk sen sdi/sdio dac offset registers gain registers configuration register cisref paout paoutn r g b oen adcclk r g b mux mux sel0 sel1 cds process i/p mux ctrl sdo/sms weak drive cds vref vrdc vrdb vrdt
p reliminary W6662CF publication release date: december 1998 - 3 - revision a1 5. pin descriptions pin name type description 10, 37, 44 avdd ap analog power supply. 4, 6, 8, 35, 42 avss ap analog ground. 45, 46 vrdt ao voltage reference decoupling (top). 47, 48 vrdb ao voltage reference decoupling (bottom). 1 vrdc ao voltage reference decoupling (center). 2 vref ao internal reference output. 3 vinr ai analog input, red channel. 5 ving ai analog input, green channel. 7 vinb ai analog input, blue channel. 11 cisref ai reference voltage input when cis input. 12 paout ao pga output, low speed analog monitor output for test only. 13 paoutn ao pga output (negative), low speed analog monitor output for test only. 14 cdsck1 di cds clock 1 (schmitt trigger input), reset level sampling clock. 15 cdsck2 di cds clock 2 (schmitt trigger input), data level sampling clock. 16 adcclk di a/d converter sampling clock (schmitt trigger input). 19 drvdd dp digital driver power supply. 17 drvss dp digital driver ground. 20 sel0 di channel select bit 0. 21 sel1 di channel select bit 1. 22 sclk di clock input of serial interface (schmitt trigger input). 23 sdi/sdio di/do serial interface of data input or serial interface of data input/output. 24 sdo/sms di, do serial interface of data output, serial interface mode select. 25 sen di enable signal of serial interface, active low. 26:34 dout[0:8] do data output bit, dout0 is lsb. 38:40 dout[9:11] do data output bit, dout11 is msb. 41 oen di output enable, active low. type: ap is analog power, ai is analog input, ao is analog output, dp is digital power, di is digital input, do is digital output.
p reliminary W6662CF - 4 - 6. functional descriptions figure 4 is the block diagram of w6662, it consists of three channel clamp circuit for cds mode, a multiplexer to mux 3-channel inputs and outputs to a correlated double sampling (cds), a programmable gain control and offset adjustment amplifier, a 12-bit analog-to-digital converter. bandgap reference circuit generate voltage reference signals for input signals clampping and correlated sampling use (in cds mode), for offset d/a converter and output a/d converter use. the select signals sel1 and sel0 are used to select the offset registers and gain registers, the input channels may be selected simultaneously. 6.1 clamp circuit the capacitor between the output of ccd/cis device and w6662 is used to block the dc voltage (even as high voltage). the clamp circuit is used to remove unwanted common-mode voltage in the input pixel data and to get a maximum input signal span when the input is driven by ccd device as shown in figure 6-1. the input pins of w6662 are clampped to a internal offset voltage while valid pixel signal is input. the clamp switches at three channels of figure 6-1 are turn on whenever cdsck1 goes high. figure 6-2 shows the waveform between output of ccd device and input of w6662, the voltage change on the capacitor will be clampped. the value of input capacitor is calculated as follows: t clp c max = (ron + r ccds ) ln (v c /v clptolerance ) i bias t c2i c min = dv where c max is the maximum capacitor value. c min is the minimum capacitor value. t clp is the high pulse width of the cdsck1 clock input. r on is switch resistance during clampping and is equivalent to 5k. r ccds is the source resistance of ccd device. v c is the voltage change on the input capacitor must be clampped. v clptolerance is the tolerance voltage error at the end of clampping. i bias is the input leakage current on the input of the w6662 device. dv is the maximum voltage drift on the input of the w6662 device. t c2i is the time stamp from the end of clampping point to the acture input data sampling point, equal to t c2s + t spd + t acd or may be approximated as conversion time t cvr .
p reliminary W6662CF publication release date: december 1998 - 5 - revision a1 if input capacitor value is specified as c in , the following is the equation to calculate how many lines are required before the capacitor settles to the desired accuracy after power is up: (r on + r ccds ) c in l n = ln (v ofs /v clptolerance ) pix n t clp where l n is line number. pix n is the total pixel number in one line. c in is the input capacitor value, 0.01 m f is suggestion value. v ofs is the internal offset voltage to be clampped on the input terminal of the input capacitor. fig. 6-1 equivalent circuit of clampping. r on = 5k r ccds c in input to mux v ofs w6662 ccd device i bias on when cdsck1= high 0.01uf fig. 6-2 ccd input clamp waveform. output signal from ccd input signal to w6662 v c (pixel n) (pixel n+1) t clp v clptolerance v c v datan v datan v datan+1 v datan+1 v ofs 6.2 mux and channel select the analog input signal may be three channels or single channel and is specified in configuration register. three channel input or single channel input are described as follows: the three channel input is used for red, green and blue analog signal input, selected by sel1 and sel0 signals. the channel select signals sel1 and sel0 may be 01, 10, 11 and listed as follows: sel1 = 0, sel0 = 1 is red channel input selected, red channel of gain register and offset register also selected. sel1 = 1, sel0 = 0 is green channel input selected, green channel of gain register and offset register also selected. sel1 = 1, sel0 = 1 is blue channel input selected, blue channel of gain register and offset register also selected. sel1 = 0, sel0 = 0 is reserved. the one channel input is used for black and white ccd/cis sensor or multiplexed color ccd/cis sensor output. any channel input of red, green or blue can be used, other un-used analog input must tight to v ss in s & h mode. the channel select signals sel1 and sel0 is used to select offset register and gain register only and may be 01, 10, 11, described as follows:
p reliminary W6662CF - 6 - sel1 = 0, sel0 = 1 is red channel of gain register and offset register selected. sel1 = 1, sel0 = 0 is green channel of gain register and offset register selected. sel1 = 1, sel0 = 1 is blue channel of gain register and offset register selected. sel1 = 0, sel0 = 0 is reserved. 6.3 cds vs s&h mode "cds" stands for "correlated double sampling". it is used to reduce noise generated in ccd source and to decrease the sampling error which induced from clampping voltage error. cds takes two step to sample a ccd's output pixel. in the first step, the reset level of ccd output is sampled and hold by s/h1 at the falling edge of cdsck1 signal. in the second step, the data signal of ccd output is sampled and hold by s/h2 at the falling edge of cdsck2 signal. the cds output voltage is obtained from the voltage difference of the outputs of s/h1 and s/h2. in s&h mode, the data signal of cis output is sampled and hold by s/h1 at the falling edge of cdsck2 signal and the output voltage is obtained from the voltage difference of the outputs of s/h1 and cisref pin. figure 6-3 shows the equivalent circuits of cds and s&h mode processing. fig. 6-3 the equivalent circuit of cds and s&h mode. s/h1 s/h2 cdsck1 cdsck2 + - from i/p mux to gain/offset adjust s/h1 cdsck2 + - from i/p mux to gain/offset adjust (a) cds mode. (b) s&h mode. from cisref pin 6.4 gain/offset adjustment the analog input signal after cds or s&h processed is amplified by pga gain adjustment and then shifted by offset value. the offset value will not affected by the pga gain adjustment.
p reliminary W6662CF publication release date: december 1998 - 7 - revision a1 pga gain adjustment "pga" stands for "programmable gain amplifier", it can provide analog gain for "not enough level for a/d converter" input signals. the gain value is converted from pga_code of gain register and is selected by channel select sel1 and sel0. the gain formula is: pga_code analog gain = 1 + 12 pga_code = 0 - 63 and the gain = 1 - 6.25. offset adjustment the analog signal level can be shifted by offset level and to get maximum linear region. the offset level is converted from offset value by internal d/a converter and the offset value is selected by channel select sel1 and sel0. the mapping between offset register code and offset value is as follows: offset register offset value 1111 1111 (lsb) +200 mv : : : : 1000 0001 +1.6 mv 1000 0000 0.0 mv 0000 0000 0.0 mv 0000 0001 -1.6 mv : : : : 0111 1111 -200 mv 6.5 analog monitor the analog differential signal of paout and paoutn is used to monitor the output waveform after gain and offset adjustment process. the ccd or cis pixel rate must operate below or equal 1mhz and at most one probe loading on the paout and paoutn to get a correct voltage output. in normal operation, the paout and paoutn must be turned off by writting a specified bit on the configuration register to avoid the interference of noise and extra capacitance loading. 6.6 internal registers the registers in the w6662 is configuration register, three channel offset registers and three channel gain registers, these registers are addressed by a2, a1 and a0. the registers can be read or modified through 3-wired or four-wired serial interface. during address phase, if sdo/sms pin is low, three- wired is selected, the three-wired interface are sen, sclk and sdio signals, if sdo/sms pin is high, four-wired interface is selected, the four-wired interface are sen, sclk sdi and sdo signals. figure 6-4 shows the setting of the serial interface. for three-wired interface setting, the sdo/sms pin must connected to vss. for four-wired interface, it only need to connect a pull high resistor on the sdo/sms pin. the signal format on the serial interface is listed as follows:
p reliminary W6662CF - 8 - r/w a0 a1 a2 -- -- -- -- d0 d1 d2 d3 d4 d5 d6 d7 address phase data phase r/w is read (high) or write (low) command to access the register. a0, a1 and a2 is the address select bits of the register. d0 throuth d7 is the data bit of the register, d7 is msb and d0 is lsb. the address of the registers is: a2 a1 a0 register 0 0 0 configuration register 0 0 1 red pga register 0 1 0 green pga register 0 1 1 blue pga register 1 0 0 red offset register 1 0 1 green offset register 1 1 0 blue offset register 1 1 1 reserved configuration register the bit definition of configuration register is: a. configuration mode (wake up and configuration) bit 0 = 0: 1.5v input span. 1: 3.0v input span. bit 1 = 0: s&h mode. 1: cds mode. bit [3:2] = 0 0: red channel input only. 0 1: green channel input only. 1 0: blue channel input only. 1 1: three channels input and selected by sel1 and sel0 signals. bit 4 = reserved (must set to 0). bit 5 = 0: paout and paoutn enable. 1: paout and paoutn disable. bit 6 = reserved (must set to 0). bit 7 = 0.
p reliminary W6662CF publication release date: december 1998 - 9 - revision a1 b. power down mode bit [6:0] = don't care. bit 7 = 1. the cdsck1, cdsck2, adcclk and sclk must hold at stable state after power down mode has been configured to ensure the w6662 is in low power state. the system must wait at least 10 ms to ensure that the device is power up completedly if the configuration register is programmed with bit 7 = 0. pga registers the mapping of pga registers and pga_code is: bit [5:0] pga_code, bit 5 is msb, bit 0 is lsb. bit [7:6] reserved (must set to 0). the offset registers are described in pga gain/offset adjustment section. fig. 6-4 configuration serial interface modes. (a). three-wired interface mode selected. (b). four-wired interface mode selected. w6662 sclk sen sdio sms micro-controller or system controller or core chip may drive another peripherals chip select w6662 sclk sen sdi sdo may drive another peripherals chip select micro-controller or system controller or core chip drvdd
p reliminary W6662CF - 10 - 7. electrical characteristics 7.1 maximum ratings* parameter symbol rating units supply voltage with respect to avss (at avdd pin) v avdd -0.3 to 6 v supply voltage with respect to drvss (at drvdd pin) v drvdd -0.3 to 6 v voltage on any pin other than v avdd supplies -0.3 to v avdd + 0.3 v voltage on any pin other than v drvdd supplies -0.3 to v drvdd + 0.3 v current at any pin other than supplies 0 to 10 ma storage temperature t st -65 to 150 c * exceeding these values may cause permanent damage. 7.2 recommended operating conditions parameter symbol rating unit operation voltage (referenced to avss pin) v avdd 4.75 to 5.25 v operation voltage (referenced to drvss pin) v drvdd 3.0 to 5.25 v operation temperature t op 0 to 70 c 7.3 power supply characteristics parameter condition symbol min. typ ? max. units test standby supply current power supply i ddq 0.1 ma test 1 operating supply current (v dd = 5.0v) i dd 30 40 ma test 2 ? : typical figure are at v dd = 5v and temperature = 25 c and are for design aid only, not guaranteed and not subject to production testing. test 1: all input pins are v dd or v ss , include cdsck1, cdsck2, adcclk and sclk, oen and sen are v dd , configure as power down mode, output without loading. test 2: no analog input, cds mode configured, 2 mhz pixel rate, paout and paoutn disabled and output without loading. 7.4 digital characteristics parameter condition sym. min. typ ? max. units notes output high sourcing current (v drvdd = 5v) i oh 0.5 ma 1 output low sinking current (v drvdd = 5v) i ol 0.5 ma 2 high level input voltage (v drvdd = 5v) v ih 2.0 v 3 low level input voltage (v drvdd = 5v) v il 0.8 v 3 schmitt input high threshold voltage (v drvdd = 5v) v t+ 2.2 v 4
p reliminary W6662CF publication release date: december 1998 - 11 - revision a1 7.4 digital characteristics, continued parameter condition sym. min. typ ? max. units notes schmitt input low threshold voltage (v drvdd = 5v) v t- 0.8 v 4 input current iin 1 m a input capacitance cin 10 pf ? : typical figure are at v dd = 5v and temperature = 25 c and are for design aid only, not guaranteed and not subject to production testing. notes: 1: v oh = 0.9 v drvdd. 2: v ol = 0.1 v drvdd. 3. all digital input pin, cdsck1, cdsck2, adcclk and sclk are exclusive. 4. cdsck1, cdsck2, adcclk and sclk schmitt trigger input pins. 7.5 analog characteristics (measures from analog input to adc output) parameter sym. min. typ ? max. units test conditions analog to digital converter maximum conversion rate sps 3 mhz resolution 12 bits integral nonlinearity inl +/- 4 lsb differential nonlinearity dnl +/- 1 lsb gain error adg err 2.7% fsr note 1 offset error adof err 2.7% fsr note 1 pga & offset dac pga gain range g 1 6.25 v/v pga gain resolution g res 64 steps note 2 offset range ofs -200 200 mv v avdd = 5.0v offset resolution ofs res 256 steps note 2 bandgap reference voltage reference tolerance (v ref = 1.5v or 0.75v) v ref +/- 1.5% +/- 2.0% v avdd = 5.0v analog input and output linear region of analog input vin 0 3 v input capacitance cin 10 pf input leakage current i bias 0.01 m a total output noise at pga 4 lsb
p reliminary W6662CF - 12 - 7.5 analog characteristics (measures from analog input to adc output), continued parameter sym. min. typ ? max. units test conditions signal to noise ratio from analog i/p to adc o/p snr 57 db note 3 ? : typical figure are at v dd = 5v and temperature = 25 c and are for design aid only, not guaranteed and not subject to production testing. notes: 1: 3v input span configured, pga gain = 1, offset = 0 and measures from analog input to adc output. 2: all steps of pga gain and offset are monotonic. 3. 3v input span configured and analog 3v signal range. 7.5.1 analog characteristics (measures from adc input to adc output) parameter sym. min. typ. max. units test conditions analog to digital converter maximum conversion rate sps 3 mhz resolution 12 bits integral nonlinearity inl +/- 1.5 lsb note differential nonlinearity dnl +/- 1 lsb note note: this is measured on the engineer sample and do not subject to production testing. 7.6 timing characteristics parameter sym. min. typ. max. units notes clock input requirement conversion rate t cvr 332 ns adcclk high pulse width t adch 166 ns adcclk low pulse width t adcl 166 ns clamp pulse width t clp 40 ns sample data pulse width t spd 40 ns clamp to sample t c2s 20 ns sample data to adc convert t s2ad 80 ns adc convert to clamp t s2c t s2ad +20 ns analog signal capture delay of cds clocks t acd 10 ns
p reliminary W6662CF publication release date: december 1998 - 13 - revision a1 7.6 timing characteristics, continued parameter sym. min. typ. max. units notes data output digital output delay t dod 40 ns output enable to data delay t oed 20 ns output disable to data tri-state t odz 20 ns digital output latency 3 adcclkcycles serial interface maximum sclk frequency f sclk 24 mhz sen to sclk set-up time t ses 10 ns sclk to sen hold time t seh 10 ns sdi input to sclk set-up time t sis 15 ns sclk to sdi input hold time t sih 10 ns sclk falling to sdo output enable time t soe 10 ns sdo output delay time t sod 15 ns sen to sdo output tri-state delay time t soz 10 ns fig. 7-1 timing of cds mode. analog input cdsck2 adcclk dout cdsck1 t acd t clp t c2s t spd t s2ad t s2c t cvr t adch t adcl (pix n+1 ) (pix n ) (pix n+2 ) t dod (pix n-3 ) (pix n-2 ) (pix n+3 ) (pix n-1 ) (pix n ) (pix n-4 ) t acd (pix n-5 ) (pix n+4 ) 1 0 2 3 latency
p reliminary W6662CF - 14 - fig. 7-2 timing of s&h mode. analog input cdsck2 adcclk dout cdsck1 t acd t spd t s2ad t cvr t adch t adcl (pix n+1 ) (pix n ) (pix n+2 ) t dod (pix n-3 ) (pix n-2 ) (pix n+3 ) (pix n-1 ) (pix n ) (pix n-4 ) (pix n-5 ) (pix n+4 ) 1 0 2 3 latency fig. 7-3 output enable timing. adcclk dout oen t dod t odz t oed high-z fig. 7-4 serial interface write timing (3-wired or 4-wired interface). sclk sdi/ sdio sen t sis t sih t seh a0 a1 a2 d0 d1 d2 d3 d4 d5 d6 d7 t ses t sis t sih 1/f sclk
p reliminary W6662CF publication release date: december 1998 - 15 - revision a1 fig. 7-5 serial interface read timing in 3-wired interface (sms = low). sclk sdio (input) sen t sis t sod t seh a0 a1 a2 t ses t sis t sih 1/f sclk sdio (output) d0 d1 d2 d3 d4 d5 d6 d7 high-z t soz t soe high-z fig. 7-6 serial interface read timing in 4-wired interface mode. sclk sdi sen t sis t sod t seh a0 a1 a2 t ses t sis t sih 1/f sclk sdo (output) d0 d1 d2 d3 d4 d5 d6 d7 high-z t soz t soe sms (input) pull-high d0 d1 d2 d3 d4 d5 d6 d7 driven by sdo (note: sdo and sms at the same pin)
p reliminary W6662CF - 16 - 8. application circuits 8.1 system application figure 8-1 is the application block diagram of scanner, the photo sensor may be ccd device or cis device with single channel or three-channel analog output. the asic is used to generate the request signal of photo sensor, w6662, motor control and other mechanical/electric interface. the memory buffer is used to temporary store the image data and the data will be transfered to the host through epp port or other interface as scsi. if micro controller is included, some control sequence, photo sensor calibration or image data procession can be completed without the aid of the host. photo sensor w6662 scanner asic host interface memory buffer micro controller (optional) fig. 8-1 system application. to/from other mechanical control and senor
p reliminary W6662CF publication release date: december 1998 - 17 - revision a1 8.2. decoupling circuit figure 8-2 shows the decoupling capacitor request on the w6662 system board to reduce noise and distortion, 0.1 m f capacitor must as near to the pin as possible. the analog power source and digital power source (drvdd) had better regulated by different regulator, the analog ground and digital ground (drvss) must separated and must connected only at one point near the power supplier. all the analog power pins must connected as short as possible and all the analog ground pins must connected as short as possible on the pc board. termination resistor must added near the w6662 chip on the cdsck1, cdsck2 and adcclk input pin. fig. 8-2 decoupling capacitor circuit of w6662 device. w6662 (analog part) (digital part) vrdt vrdt 0.1uf 0.1uf 0.1uf vdrb vrdb 10uf + vrdc 0.1uf vref 0.1uf 1uf + cisref 0.1uf 0.1uf 10uf + avdd avss avdd (other pins are not shown) 10uf + 0.1uf drvdd drvss drvdd (near power source) cdsck1 cdsck2 adcclk r term r term r term
p reliminary W6662CF - 18 - 9. package dimensions 48l qfp (10 x 10 x 2.0 mm footprint 5.0 mm) 0.20 0.10 0.008 0.004 symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.15 0.004 0.010 0.078 0.013 0.018 0.25 0.10 2.00 0.33 0.45 0.390 0.098 0.004 0 10 0.394 0.066 0.398 9.9 0.75 2.50 10.00 1.70 10.1 0.398 0.394 0.390 0.598 0.590 0.582 15.20 15.0 14.80 10.1 10.00 9.9 10 0 0.10 .029 0.008 0.012 0.20 0.30 seating plane 12 13 see detail f 24 e b a y 1 a 2 l l 1 c e e h 1 d 48 h d 37 36 detail f 0.90 2.30 0.598 0.590 0.582 15.20 15.0 14.80 25 q q
p reliminary W6662CF publication release date: december 1998 - 19 - revision a1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792646 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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